Conventionally, as semiconductor devices having a switching function, MOSFETs (metal oxide semiconductor field-effect transistors) are known (e.g., see Patent Document 1 listed below). Patent Document 1 discloses a trench-gate type MOSFET (semiconductor device) having a gate electrode buried in a trench formed in a semiconductor layer of one conductivity type.
FIG. 33 is a sectional view showing the structure of the conventional MOSFET (semiconductor device) disclosed in Patent Document 1 mentioned above. Referring to FIG. 33, in the conventional MOSFET, on the top face of an n+ type semiconductor substrate 501, an epitaxial layer 502 is formed. In the epitaxial layer 502, there are formed, in order from the semiconductor substrate 501 side, an n− type doped region (drain region) 502a, a p type doped region 502b, and n+ type doped region (source region) 502c. 
In the epitaxial layer 502, a trench 503 is formed which penetrates through the n+ type doped region 502c, through the p type doped region 502b, and halfway through then type doped region 502a down to a depth somewhere within its depth. Inside the trench 503, a gate electrode 505 is formed, with a gate insulation film 504 interposed in between. In a predetermined region on the top face of the epitaxial layer 502, an interlayer insulation film 506 is formed which stops the opening of the trench 503.
On the top face of the epitaxial layer 502, a source electrode 507 is formed so as to cover the interlayer insulation film 506. On the back (bottom) face of the semiconductor substrate 501, a drain electrode 508 is formed. It is to be noted that capacitors are parasitically formed, one between the gate electrode 505 and the source electrode 507 and another between the gate electrode 505 and the drain region 502a. 
In the conventional semiconductor device configured as described above, on/off control is achieved by varying the voltage applied to the gate electrode 505. Specifically, when a predetermined positive potential is applied to the gate electrode 505, the minority carriers (electrons) in the p type doped region 502b are attracted toward the trench 503, and as a result an inversion layer 509 is formed so as to connect the n− type doped region (drain region) 502a and the n+ type doped region (source region) 502c together. This enables a current to pass through the inversion layer 509 between the source electrode 507 and the drain electrode 508. Consequently, the MOSFET goes into an ON state. In this way, in the conventional MOSFET, the inversion layer 509 that is formed so as to connect then type doped region (drain region) 502a and the n+ type doped region (source region) 502c together is utilized to function as a channel.
On the other hand, when the predetermined positive potential stops being applied to the gate electrode 505, the inversion layer (channel) 509 disappears, and this permits the current between the source electrode 507 and the drain electrode 508 to be cut off. Consequently, the MOSFET goes into an OFF state.    Patent Document 1: JP-A-2001-7149.